| 업무내용/자격요건 |
[담당업무]
DT (경력 5년이상)
∙ Work closely with Design Flow team at company headquarters to gain a deep understanding of
design methodology & flow, technology capabilities and constraints.
∙ Good knowledge in script/programming languages such as Perl, Python, TCL, C/C+
∙ Experience with complete ASIC or Standard Product Implementation flow
- 4+ years RTL Synthesis/Timing Constratint Creation, Analysis and Closure
- 4+ years Floorplan/Place/Route and related work
- Proficiency with design tools, flows and Tcl/Perl/Python script language
∙ 5+ years of hands on experience on RTL2GDSII or supporting SoC designs for the same including
converging and taping out multi-Ghz SoC design partitions with multiple power domains on
leading edge process technology (10nm/5nm/3nm or more advanced)
[자격요건]
- 경력 5년이상
∙ 공학전공 (석박사 우대)
Bachelor’s Degree in Electrical Engineering, Computer Engineering,
Computer Science, or related field
∙ 외국어 회화 가능자 우대
∙ Design Flow/Design Methodology 관련 경력 우대
[전형절차]
서류 - 1차면접 - 2차면접
[제출서류]
브레인센터 이력서 양식(사진포함) |